1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a ferroelectric memory device including a memory cell that includes a ferroelectric capacitor and a transistor.
2. Description of the Related Art
The ferroelectric memory (FeRAM) is a semiconductor memory device that uses the hysteresis characteristics of the ferroelectric capacitor to allow for binary data storage in a non-volatile manner using the two different polarization strengths of the ferroelectric substance. The memory cell of the conventional ferroelectric memory generally adopts a similar architecture to the DRAM. The cell replaces the dielectric capacitor with the ferroelectric capacitor, providing a set of the ferroelectric capacitor and the transistor connected in series (see, for example, JP 2001-250376). A plurality of the sets form the memory cell array.
There are two schemes of reading data from the ferroelectric memory: a two transistor/two cell scheme (2T2C scheme) that reads 1-bit data from two memory cells and a one transistor/one cell scheme (1T1C scheme) that reads 1-bit data from one memory cell.
The 1T1C scheme selects a word line of the cell to be read, and renders the selection transistor conductive, thereby connecting the memory cell and a bit line. A plate voltage is then applied to a plate line connected to the memory cell, and a voltage is applied across the ferroelectric capacitor included in the memory cell. The charge is read from the ferroelectric capacitor to the bit line. The bit line forms a bit-line pair with another bit line (complementary bit line). The complementary bit line is applied with a reference potential from a reference-potential generation circuit.
A sense amplifier amplifies the difference between the bit-line pair potentials. The difference of the charge read to the bit-line pair provides a signal. The signal depends largely on the ratio of the bit-line capacitance Cb and the ferroelectric-capacitor capacitance Cs. Unfortunately, as the memory cells become smaller, the bit-line capacitance generally increases, thus reading a smaller signal to the bit-line pair and decreasing the operation margin. The sense amplifier capacitance Csa has not been as much improved as the memory cells become smaller. The capacitance Csa thus generally has relatively more effect on the read-signal amplitude and the read-operation margin as the memory cells become smaller.